Responsibilities

• Evaluate the PPA of our design as part of the chip architecture planning process.
• Perform synthesis, logic equivalence checking, SDC & UPF development, and static timing analysis.
• Work collaboratively with a design house to achieve the best outcome.

Minimum Qualifications

• Bachelor’s degree in Electronic Engineering or other technically related fields
• Experience with using Verilog HDL for digital logic design
• 2+ years of industry experience with logic synthesis, LEC, STA, producing SDC & UPF
• Experience with EDA tools (Synopsys tool chain, DC, FM, PT) and scripting (TCL, shell)

Preferred Qualifications

• 5+ years of industry experience with ASIC design
• DFT, Place and Route experience
• Experience with high-speed connectivity IPs (e.g., PCIe, Ethernet, HBM)

Contact

• recruit@furiosa.ai